//******************************************************************************
//SerialRxManager	-	Module to handle input from serial port to parallel
//							representation for other modules
//						Input bytes are divided into to nibbles:
//							rx_data[7:4]	- Address nibble
//							rx_data[3:0]	- Data nibble
//						This makes for 16 addressable sets of registers, each 4
//							bits wide, or 8 bytes.
//						Uses the asynchronous serial receiver module by Jean
//							from fpga4fun.com KNJN LLC.
//
//By				-	Yi Yao			http://yyao.ca/
//Date				-	2005-12-27
//******************************************************************************


module SerialRxManager(rx, outdata, clk);
	input	rx;
	output	[63:0] outdata;
	input	clk;

	wire	data_ready;
	wire	[7:0] rx_data;

	reg	[3:0] mem [15:0];

	async_receiver (.clk(clk), .RxD(rx), .RxD_data_ready(data_ready),
			.RxD_data(rx_data));

	always @ (posedge clk) begin
		if (data_ready) begin
			mem[rx_data[7:4]] <= rx_data[3:0];
		end
	end

	assign outdata[3:0] = mem[0];
	assign outdata[7:4] = mem[1];
	assign outdata[11:8] = mem[2];
	assign outdata[15:12] = mem[3];
	assign outdata[19:16] = mem[4];
	assign outdata[23:20] = mem[5];
	assign outdata[27:24] = mem[6];
	assign outdata[31:28] = mem[7];
	assign outdata[35:32] = mem[8];
	assign outdata[39:36] = mem[9];
	assign outdata[43:40] = mem[10];
	assign outdata[47:44] = mem[11];
	assign outdata[51:48] = mem[12];
	assign outdata[55:52] = mem[13];
	assign outdata[59:56] = mem[14];
	assign outdata[63:60] = mem[15];
endmodule